1. Field of the Invention
The present invention relates generally to semiconductor packages and manufacturing methods thereof. More particularly, the invention relates to semiconductor packages with integrated metal pillars and manufacturing methods thereof.
2. Description of Related Art
A conventional flip chip package typically includes a substrate, conductive solder, a chip, and an underfill material. The substrate can be an organic substrate having an upper surface, at least one substrate pad, and a solder mask layer. The solder mask layer can have an opening so as to expose part of the substrate pad. The chip typically includes a chip body, a chip pad, a passivation layer, and at least one under ball metal layer. The conductive solder can be disposed between the substrate pad and the under ball metal layer to form electrical and mechanical connections. The underfill material can be filled into the space between the substrate and the die to protect the solder connections.
Typically, the chip has metal layers and interlayer dielectric layers formed adjacent to the silicon chip body. As the width of wires on the chip narrows and as the density of the circuit increases, the dielectric constant (k) of the dielectric layer can be reduced, so as to reduce the effects of leakage current of the circuit, capacitance effects between wires, and heat produced by the circuit. Dielectric layers can be classified as: standard k (4.5<k<10), low k (k<3.0), ultra low k (2.0<k<2.5), and extremely low k (k<2.0). A dielectric layer having ultra low k or extremely low k can be used in a 45 nanometer process. A typical method of forming an ultra low k and extremely low k dielectric layer is to make the dielectric layer porous with voids dispersed randomly within a contiguous solid dielectric.
However, in a conventional structure including conductive solder, a pitch corresponding to a certain distance is maintained between substrate pads and between chip pads, to prevent the conventional structure from becoming a short circuit during a reflow process of the conductive solder. This can limit the extent to which a package having the conventional structure can be miniaturized.
Furthermore, the strength of the dielectric layer decreases as the dielectric constant (k) decreases. The ultra low k and extremely low k dielectric layers tend to have low tensile strength, which can result in cracking at lower values of tensile stress than for higher k dielectric layers.
It is against this background that a need arose to develop the semiconductor package and related methods described herein.